The present invention relates to a semiconductor device and, more particularly, to a semiconductor IC (Integrated Circuit) device having a dynamic bias test (BT) capability.
A semiconductor IC device with a dynamic BT capability is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 7-198796. The IC device taught in this document is constructed to effect a dynamic BT without resorting to a clock or various control signals input from an external pattern generator and thereby reduce the dynamic BT cost. However, the conventional IC device has some problems left unsolved, as follows. First, the IC device includes a semiconductor IC having a plurality of internal pattern generators and a plurality of switches exclusively assigned to a dynamic BT, resulting in a great amount of exclusive hardware for a dynamic BT. Second, such exclusive internal pattern generators and switches each must be interconnected by particular signal wiring, increasing the total wiring length in the IC. Third, the switches intervening between an input terminal and the internal circuitry of the IC aggravates a circuit delay time and a wiring delay time at the output wirings of the switches.
Technologies relating to the present invention are also disclosed in, e.g., Japanese Patent Laid-Open Publication No. 58-96744, 2-257650, 4-152543, 5-259284, 5-288808, 6-138191, 6-148289, 7-128400, and 7-294606.